As the FPGA reconfigurable technology emerges, the conventional embedded design approach is greatly changed. As a new computing pattern in time-space domain, reconfigurable computing has wide application prospects in the embedded and high-performance computing field, and has become the developing trend of embedded systems now. The development of local dynamic reconfigurable technique represents a new reconfigurable design concept, and mainly consists of reconfigurable hardware and reconfigurable configuration control units that manage the functional reconfiguration of hardware. By updating the configuration information in the reconfigurable hardware, a reconfigurable configuration control unit maps the subtasks included in the algorithm application to the computing units in the reconfigurable hardware. The reconfigurable hardware can be fine-grained FPGA logical units or coarse-grained modules with specific functions. Thus, the execution of hardware functions is more flexible, the gap between software and hardware is narrowed, and hardware tasks can be invoked and configured as required in the same flexible way as software tasks.
Recently, reconfigurable computing has been widely applied in various engineering application fields, mainly including: video image processing, digital signal processing, wireless communication, and data encryption, etc. As the requirements of software applications become increasingly higher, the requirements for performance of reconfigurable systems become higher and higher. For example, the criterion for video decoding has evolved to 1080p or even higher, and the volume of code stream to be processed as per 1080p criterion is 5 times of the volume of code stream to be processed as per D1 criterion. Accordingly, as compared with applications in which D1 decoding is carried out, the processing performance of the reconfigurable system has to be 5 times as high as the former when 1080p decoding is carried out. The processing performance of a reconfigurable system is codetermined by the computing performance and reconfiguration performance of the reconfigurable hardware. The computing performance reflects the execution efficiency of each of the subtasks in the reconfigurable hardware, while the reconfiguration performance reflects the reconfiguration efficiency during functional switchover among the subtasks in the reconfigurable hardware. The requirements for improved reconfiguration performance mainly come from the following two aspects: on one hand, to improve the computing performance of a reconfigurable system, the computing units included in the reconfigurable system have to be escalated; consequently, the number of computing units to be reconfigured in the reconfigurable system becomes larger and larger. Accordingly, the data volume of configuration information required in the reconfiguration process is further increased, and the time required for dynamic reconfiguration is increased. On the other hand, to maximize the utilization of hardware computing resources in the reconfigurable system, the functions of the computing units have to be reconfigured frequently, so as to accomplish mapping of different tasks in the shortest time. Therefore, the time required for dynamic reconfiguration has to be reduced as much as possible. The improvement of computing performance of reconfigurable hardware can be implemented by adding more computing units and increasing the level of parallel computing among tasks. The key for optimizing the reconfiguration performance of a reconfigurable system is to improve the configuration information access efficiency in the reconfigurable system. However, how a local dynamic reconfigurable system can utilize the characteristics of the algorithm application to improve the configuration information access efficiency in the reconfigurable system has become a factor that constrains the development of reconfigurable technology.
In the design of a reconfigurable system, usually the configuration information is cached in on-chip configuration information caches, in order to optimize the configuration information access process. Therefore, the cache management method for configuration information determines the efficiency of dynamic reconfiguration. In a conventional reconfigurable system, the cache structure for configuration information storage is a centralized structure all reconfigurable arrays share one large configuration information cache) or a distributed structure (i.e., each reconfigurable array is closely coupled with a small configuration information cache). In the centralized configuration information cache structure, the shared configuration information cache encounters frequent access conflicts resulted from access from multiple reconfigurable arrays; consequently, the configuration information access efficiency is lowered. In the distributed configuration information cache structure, the utilization ratio of configuration information caches is lowered, owing to the fact that several configuration information caches store the same configuration information. Moreover, in the conventional cache management model for reconfigurable system configuration information, it is impossible to effectively use the configuration information caches and improve the configuration information access efficiency by utilizing the characteristics of the algorithm. As a result, the improvement of reconfiguration performance and processing performance of the reconfigurable system is limited.